Dr. Akshay K. received a B.Tech degree in Electronics and Communication Engineering from NIT Calicut, in 2017 and an accelerated Ph.D. with M.S. in Electrical Engineering from IIT Madras in 2022 with Prime Minister’s Research Fellowship. His research interests include the design, and development of (a) power semiconductor devices based on silicon carbide as well as emerging materials like diamond, and (b) flash memory cells. He is the recipient of the Institute Research Award issued by IIT Madras and AWSAR Award issued by DST, Govt. of India. Prior to joining IIT Bhubaneswar he was a Senior Semiconductor Device Engineer in the Technology Development Group at Micron Technology Inc., where he was involved in the design and optimization of biasing schemes for next-generation non-volatile 3D-NAND flash memory transistor arrays.

Theory Courses

1. Power Semiconductor Devices (Jan-May 2025)
2. VLSI Design (Jan-May 2024)
3. Microprocessor and Microcontroller (Jul – Nov 2023)

Laboratory Courses

1. VLSI Design Lab (Jan-May 2024 & 2025)
2. Microprocessor and Microcontroller Lab (Jul – Nov 2023)
3. Electrical Technology Lab (Jul- Nov 2023)

1. Singh, S.Karmalkar, and K. Akshay, “Humidity and Ring Spacing Variation Tolerant Design of a SiC Power MOSFET Using Mirrored Floating Field Rings”, Microelectronics Journal, vol. 158, p. 106611, Apr. 2025.
2. Singh, S.Karmalkar, and K. Akshay, “Improved Short Circuit Performance of Silicon Carbide VD-MOSFETs Using an Additional P+ Implant”, Microelectronics Reliability, vol. 166, pp.115614, Apr. 2025.
3. Mahalik, K. Akshay, S. Dey, “A 2D-MoS₂-Based Thin-Film Transistor for Trace-Level SO₂ Monitoring,” IEEE Transactions on Electron Devices, vol. 72, no. 1, pp. 390-396, Jan. 2025.
4. Anuvindh R, S. Mahalik, A. Roy, Akshay, S. Dey, “Conductance Spectroscopy: A Novel Technique for Ultra Selective Chemical Detection,” IEEE Sensors Journal, vol. 24, no. 24, pp. 40417 – 40422, Nov. 2024.
5. K. Akshay and S. Karmalkar, “Optimum Aspect Ratio of Superjunction Pillars Considering Charge Imbalance,” IEEE Transactions on Electron Devices, vol. 68, no. 4, pp. 1798-1803, Apr. 2021.
6. K. Akshay and S. Karmalkar, “Improved Theoretical Minimum of the Specific On-Resistance of a Superjunction,” Semiconductor Science and Technology, vol. 36, no. 1, p. 015021, Dec. 2020.
7. K. Akshay and S. Karmalkar, “Note Clarifying “Charge Sheet Super Junction in 4H-Silicon Carbide: Practicability, Modeling and Design”,” IEEE Journal of the Electron Devices Society, vol. 8, pp.1315-1316, Oct. 2020.
8. K. Akshay and S. Karmalkar, “Charge Sheet Super Junction in 4H-Silicon Carbide: Practicability, Modeling and Design,” IEEE Journal of the Electron Devices Society, vol. 8, pp. 1129-1137, Sep. 2020.
9. K. Akshay and S. Karmalkar, “Quick Design of a Superjunction Considering Charge Imbalance Due to Process Variations”, IEEE Transactions on Electron Devices, vol. 67, no. 8, pp. 3024 3029, Aug. 2020.
10. M. G. Jaikumar, K. Akshay, and S. Karmalkar, “An algorithm to design floating field rings in SiC and Si power diodes and MOSFETs”, Solid-State Electronics, vol.156, pp.73-78, Jun. 2019.

1. K. J. Swadhin, P. Chiranjeebi, K.Akshay, P.V. Satyam, “Investigation of Al2O3/SiO2 Interface Charge for the Feasibility Study of Charge Sheet Super Junction”, in Proc. IEEE Electron Devices Technology & Manufacturing Conference, 2025.
2. Mrinmoy, K. Prathamesh, and K. Akshay, “TCAD based Study of String Current Variability in 3D NAND Flash Memory”, in Proc. 38^th IEEE International Conference on VLSI Design, 2025.
3. P. Singh, K. Akshay, H.L.R. Maddi, A. Agarwal, S. Karmalkar, Design of the Drift Layer of 0.6-1.7 kV Power Silicon Carbide MOSFETs for Enhanced Short Circuit Withstand Time, in Proc. IEEE Electron Devices Technology & Manufacturing Conference, 2023. DOI: 10.1109/EDTM55494.2023.10103006
4. K. Akshay, M. G. Jaikumar and S. Karmalkar, Charge Sheet Super Junction in 4H-Silicon Carbide, in Proc. IEEE Electron Devices Technology & Manufacturing Conference, 2020. DOI: 10.1109/EDTM47692.2020.9117845
5. K. Akshay, R. P. Parvathy, and B. Bhuvan, Enhancement of Full Well Capacity of a Pinned Photodiode, International Workshop on the Physics of Semiconductor Devices, 2019.
6. K. Akshay, M. Moun, R. Singh, and S. Karmalkar, TCAD Simulation of the Measured I-V Behaviour of Schottky Contacts on Exfoliated MoS2 Flakes, IEEE International Conference on Emerging Electronics, 2018.
7. K. Akshay, R. P. Parvathy, and B. Bhuvan, System Level Design of a Novel CMOS Image Sensor with High Dynamic Range and Fill Factor, in Proc. IEEE TENCON, 2019. DOI: 10.1109/TENCON.2019.8929325
8. K. Akshay, R. P. Parvathy, and B. Bhuvan, Analytical Modeling of Response Time and Full Well Capacity of a Pinned Photo Diode, in Proc. IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2018. DOI: 10.1109/DTIS.2018.8368568
9. K. Akshay, R. P. Parvathy, and B.Bhuvan, Optimum length of a pinned photodiode, in Proc. IEEE International Conference on Electron Devices and Solid-State Circuits, 2017. DOI: 0.1109/EDSSC.2017.8126451

Post-PhD Experience

• Assistant Professor                        Oct 2023 – Present
  • School of Electrical and Computer Sciences, Indian Institute of Technology Bhubaneswar
  • Consultant to multiple power device companies and also the Principal Investigator of multiple government and industry projects
  • Currently supervising three Ph.D scholars, teaching one theory course and two labs.

• Director and Co-Founder            Apr 2024 – Present
  • Nano Semic Pvt. Ltd.: Company based on semiconductor products and service

• Visiting Assistant Professor                    May 2023 – Oct 2023
  • School of Electrical Sciences, Indian Institute of Technology Bhubaneswar

• Senior Engineer NAND Device, Technology Development                            Aug 2022 – Mar 2023
  • Micron Technology, Inc.: Responsible for the design and optimization of biasing schemes for next-generation non-volatile 3D-NAND flash memory transistor arrays.

• Post-Doctoral Fellow       May 2022 – July 2022
  • IIT Madras: Appointed for submitting the Ph.D. thesis within 5 years.
  • Proposed a novel drift layer design method for increasing the breakdown voltage of SiC-Power MOSFETs by up to 68 % with just 6% increase in specific on-resistance. This work was done in collaboration with Prof. Anant Agarwal’s group at Ohio State University.
  • Internships and research assignments in collaboration with several leading academic groups in abroad (in Ohio State University, Purdue University) and India (in IIT Delhi, IISc, and NIT Calicut), industry (RIR Power Electronics Ltd.) , and research lab (SSPL under DRDO).

Administrative Responsibilities @ IIT Bhubaneswar

• UG Coordinator of Department of ECE                                                            October 2024-Present                                                                                                                
•  Professor in Charge (IDEA Lab)                                                                         July 2024 – Present                                                                                                                
•  Professor in Charge (Micro Fabrication and Characterization Lab)   May 2024 – Present                                                                                                                
• Faculty Coordinator for Placements and Internships (ECE)                    May 2024 – Present                                                                                                                
• SES Aesthetics Committee Member                                                                    May 2024 – Present