Dr. Akshay K.
Assistant Professor
- Room No: A-007, SECS
- +91 674713-5784
- akshay@iitbbs.ac.in
- School of Electrical and Computer Sciences
Dr. Akshay K. received a B.Tech degree in Electronics and Communication Engineering from NIT Calicut, in 2017 and an accelerated Ph.D. with M.S. in Electrical Engineering from IIT Madras in 2022 with Prime Minister’s Research Fellowship. His research interests include the design, and development of (a) power semiconductor devices based on silicon carbide as well as emerging materials like diamond, and (b) flash memory cells. He is the primary contributor in over a dozen publications in leading international journals and conferences. He is the recipient of the Institute Research Award issued by IIT Madras and AWSAR Award issued by DST, Govt. of India. Prior to joining IIT Bhubaneswar he was a Senior Semiconductor Device Engineer in the Technology Development Group at Micron Technology Inc., where he was involved in the design and optimization of biasing schemes for next-generation non-volatile 3D-NAND flash memory transistor arrays.
- Microprocessor and Microcontroller (Jul – Nov 2023)
- Microprocessor and Microcontroller Lab (Jul – Nov 2023)
- Electrical Technology Lab (Jul- Nov 2023)
| Name | Tenure | Role | Topic |
| Rachita Mohapatra | Jul 2023-Ongoing | Supervisor | SiC Superjunction Devices |
| Swadhin Kumar Jena | Jan 2023-Ongoing | Co-Supervisor | Investigation of Al2O3/SiO2 Bilayer on Si and SiC Substrates for Power Device Applications |
- K. Akshay and S. Karmalkar, Optimum Aspect Ratio of Superjunction Pillars Considering Charge Imbalance, vol. 68, no. 4, pp. 1798-1803, Apr. 2021. DOI: 10.1109/TED.2021.3060684
- K. Akshay and S. Karmalkar, Improved Theoretical Minimum of the Specific On-Resistance of a Superjunction, Semiconductor Science and Technology, vol. 36, no. 1, p. 015021, Dec. 2020. DOI: 10.1088/1361-6641/abc921
- K. Akshay and S. Karmalkar, Note Clarifying “Charge Sheet Super Junction in 4H-Silicon Carbide: Practicability, Modeling and Design”, IEEE Journal of the Electron Devices Society, vol. 8, pp.1315-1316, Oct. 2020. DOI: 10.1109/JEDS.2020.3031916
- K. Akshay and S. Karmalkar, Charge Sheet Super Junction in 4H-Silicon Carbide: Practicability, Modeling and Design, IEEE Journal of the Electron Devices Society, vol. 8, pp. 1129-1137, Sep. 2020. DOI: 10.1109/JEDS.2020.3021827
- K. Akshay and S. Karmalkar, Quick Design of a Superjunction Considering Charge Imbalance Due to Process Variations, IEEE Transactions on Electron Devices, vol. 67, no. 8, pp. 3024 3029, Aug. 2020. DOI: 10.1109/TED.2020.2998443
- M. G. Jaikumar, K. Akshay, and S. Karmalkar, An algorithm to design floating field rings in SiC and Si power diodes and MOSFETs, Solid-State Electronics, vol.156, pp.73-78, Jun. 2019. DOI: 10.1016/j.sse.2019.03.025
- P. Singh, K. Akshay, H.L.R. Maddi, A. Agarwal, S. Karmalkar, Design of the Drift Layer of 0.6-1.7 kV Power Silicon Carbide MOSFETs for Enhanced Short Circuit Withstand Time, in Proc. IEEE Electron Devices Technology & Manufacturing Conference, 2023. DOI: 10.1109/EDTM55494.2023.10103006
- K. Akshay, M. G. Jaikumar and S. Karmalkar, Charge Sheet Super Junction in 4H-Silicon Carbide, in Proc. IEEE Electron Devices Technology & Manufacturing Conference, 2020. DOI: 10.1109/EDTM47692.2020.9117845
- K. Akshay, R. P. Parvathy, and B. Bhuvan, Enhancement of Full Well Capacity of a Pinned Photodiode, International Workshop on the Physics of Semiconductor Devices, 2019.
- K. Akshay, M. Moun, R. Singh, and S. Karmalkar, TCAD Simulation of the Measured I-V Behaviour of Schottky Contacts on Exfoliated MoS2 Flakes, IEEE International Conference on Emerging Electronics, 2018.
- K. Akshay, R. P. Parvathy, and B. Bhuvan, System Level Design of a Novel CMOS Image Sensor with High Dynamic Range and Fill Factor, in Proc. IEEE TENCON, 2019. DOI: 10.1109/TENCON.2019.8929325
- K. Akshay, R. P. Parvathy, and B. Bhuvan, Analytical Modeling of Response Time and Full Well Capacity of a Pinned Photo Diode, in Proc. IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2018. DOI: 10.1109/DTIS.2018.8368568
- K. Akshay, R. P. Parvathy, and B.Bhuvan, Optimum length of a pinned photodiode, in Proc. IEEE International Conference on Electron Devices and Solid-State Circuits, 2017. DOI: 0.1109/EDSSC.2017.8126451
| Degree | Discipline | Year | School |
|---|---|---|---|
| Ph.D. (with MS) | Electrical Engineering | 2022 | IIT Madras |
| B.Tech | Electronics and Communication Engineering | 2017 | NIT Calicut |
Dr. Akshay K. was a Senior Semiconductor Device Engineer at the Technology Development Group at Micron Technology Inc. from August 2022 – April 2023. In this role, he was involved in the design and optimization of biasing schemes for next-generation non-volatile 3D-NAND flash memory transistor arrays. Prior to joining Micron, he was a Post-Doctoral Equivalent Fellow(ship) at IIT Madras from May 2022 – July 2022. During his Ph.D. tenure, in addition to his core thesis problem, he did internships and research assignements in collaboration with several leading academic groups in abroad (in Ohio State University, Purdue University) and India (in IIT Delhi, IISc, and NIT Calicut), industry (RIR Power Electronics Ltd.) , and research lab (SSPL under DRDO).