School of Electrical and Computer Sciences

School of Electrical and Computer Sciences, IIT Bhubaneswar

IIT Bhubaneswar Logo

IIT Bhubaneswar

Dr. Sandeep Kumar Samal

Assistant Professor (Visiting Faculty)
  • Room No. A-008, School of Electrical and Computer Sciences, IIT Bhubaneswar
  • +91 674-7135794
  • sandeepksamal@iitbbs.ac.in
  • School of Electrical and Computer Sciences
IRINS Profile
Brief Resume
Google Scholar
Personal Website
System/Design Technology Co-optimization (STCO/DTCO), CAD for Low-Power Digital Design, 2.5D/3D ICs

Sandeep Kumar Samal (S’12-M’17-SM’23) received the B.Tech. degree in Electronics and Electrical Communication Engineering from the Indian Institute of Technology Kharagpur, Kharagpur, India, in 2012, and the Ph.D. degree in Electrical and Computer Engineering from
the Georgia Institute of Technology, Atlanta, GA, USA, in 2017. From 2017 to 2025, he worked at Intel, Oregon, USA first in the Foundry Technology Development group and then in the Altera FPGA Technology Engineering group. In the Foundry Technology Development group, he was involved in design-technology co-optimization and technology integration of Intel advanced-node processes in next-generation products, specifically process monitoring circuit design and analysis, and power-performance-area (PPA) optimization. His FPGA related work focused on technology pathfinding, system level packaging exploration, and advanced node test-chip design for next-generation FPGAs and related products. He joined the School of Electrical and Computer Sciences, IIT Bhubaneswar, India in 2025 as a Visiting Faculty.

His research interests include system/design technology co-optimization (STCO/DTCO), CAD for low power and reliable digital design, 3D ICs, and other advanced packaging techniques. His Ph.D. research focused on design and CAD for low-power and reliable monolithic 3D ICs. He also interned at Globalfoundries for one-year working on 3D IC pathfinding and exploration. He is a Senior Member of IEEE and has served as co-chair and member on the Technical Program Committee of several premier conferences in Electronic Design Automation.

IIT Bhubaneswar

  • Autumn 2025
    • Basic Electronics and Electrical Engineering (EE1L002)
    • Semiconductor Packaging and Testing (EC6L063)

Georgia Tech

  • Spring 2017: Fundamental of Digital System Design (ECE2020)
  1. Ritochit Chakraborty, Sandeep Kumar Samal, Mangesh Kushare, Jingrong Zhou, and Ashok Murugavel, “Full-chip Layout Automation for Modular Metal-Stack to Enable Process and Yield Optimization” in Intel Design and Test Technology Conference, 2024
  2. Tianchen Wang, Sandeep Kumar Samal, Sung Kyu Lim, and Yiyu Shi, “Entropy Production Based Full-Chip Fatigue Analysis: From Theory to Mobile Applications”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 38, No. 1, pp 84-95, January 2019.
  3. Tiantao Lu, Caleb Serafy, Zhiyuan Yang, Sandeep Kumar Samal, Sung Kyu Lim, and Ankur Srivastava, “TSV-based 3D ICs: Design Methods and Tools”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Keynote Paper, Vol. 36, No. 10, pp 1593-1619, October 2017.
  4. Shreepad Panth, Sandeep Kumar Samal, Kambiz Samadi, Yang Du, and Sung Kyu Lim, “Tier Degradation of Monolithic 3D ICs: A Power Performance Study at Different Technology Nodes”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol 36, No. 8, pp. 1265-1273, August 2017.
  5. Sandeep Kumar Samal, GuoQing Chen, and Sung Kyu Lim, “Improving Performance Under Process and Voltage Variations in Near-Threshold Computing Using 3D ICs”, ACM Journal of Emerging Technologies in Computing (JETC), Vol. 13, No. 4, Article 59, June 2017.
  6. Sandeep Kumar Samal, Kambiz Samadi, Pratyush Kamal, Yang Du, and Sung Kyu Lim, “Full Chip Impact Study of Power Delivery Network Designs in Gate-Level Monolithic 3D ICs”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 36, No. 6, pp. 992-1003, June 2017.
  7. Sandeep Kumar Samal, GuoQing Chen, and Sung Kyu Lim, “Machine Learning Based Variation Modeling and Optimization for 3D ICs”, Journal of Information and Communication Convergence Engineering (JICCE), Vol. 14, No. 4, pp. 258-267, 2016.
  8. Sandeep Kumar Samal, Shreepad Panth, Kambiz Samadi, Mehdi Saeidi, Yang Du, and Sung Kyu Lim, “Adaptive Regression-based Thermal Modeling and Optimization for Monolithic 3D ICs”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 35, No. 10, pp. 1707-1720, October 2016.
  9. Sandeep Kumar Samal, Yarui Peng, Mohit Pathak, and Sung Kyu Lim, “Ultralow-Power Circuit Design with Subthreshold/Near-Threshold 3D IC Technologies”, IEEE Transactions on Components, Packaging and Manufacturing Technology (TCPMT), Vol. 5, No. 7, pp. 980-990, July 2015.
  10. Shreepad Panth, Sandeep Kumar Samal, Yun Seop Yu and Sung Kyu Lim, “Design Challenges and Solutions for Ultra-High-Density Monolithic 3D ICs”, Journal of Information and Communication Convergence Engineering (JICCE), Vol. 12, No. 3, pp. 186-192, 2014.
  1. Bon Woong Ku, Yu Liu, Yingyezhe Jin, Sandeep Kumar Samal, Peng Li, and Sung Kyu Lim, “Design and Architectural Co-optimization of Monolithic 3D Liquid State Machine-based Neuromorphic Processor”, ACM Design Automation Conference (DAC), 2018.
  2. Sandeep Kumar Samal, Sourabh Khandelwal, Asif Islam Khan, Sayeef Salahuddin, Chenming Hu, and Sung Kyu Lim, “Full Chip Power Benefits with Negative Capacitance FETs”, IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2017.
  3. Jiajun Shi, Deepak Nayak, Srinivasa Banna, Robert Fox, Srikanth Samavedam, Sandeep Kumar Samal and Sung Kyu Lim, “A 14nm Finfet Transistor-Level 3D Partitioning Design to Enable High- Performance and Low-Cost Monolithic 3D IC”, IEEE International Electron Devices Meeting (IEDM), 2016.
  4. Sandeep Kumar Samal, Deepak Nayak, Motoi Ichihashi, Srinivasa Banna, and Sung Kyu Lim, “Tier Partitioning Strategy to Mitigate BEOL Degradation and Cost Issues in Monolithic 3D ICs”, IEEE International Conference on Computer-Aided Design (ICCAD), 2016.
  5. Sandeep Kumar Samal, Deepak Nayak, Motoi Ichihashi, Srinivasa Banna, and Sung Kyu Lim, “Monolithic 3D IC vs. TSV-based 3D IC in 14nm FinFET Technology”, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2016.
  6. Sandeep Kumar Samal, Deepak Nayak, Motoi Ichihashi, Srinivasa Banna, and Sung Kyu Lim, “How to Cope with Slow Transistors in the Top-tier of Monolithic 3D ICs: Design Studies and CAD Solutions”, IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2016.
  7. Sandeep Kumar Samal, Deepak Nayak, Motoi Ichihashi, Srinivasa Banna, and Sung Kyu Lim, “Impact of Transistor Technology on Power Savings in Monolithic 3D ICs”, IEEE International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2016.
  8. Tianchen Wang, Sandeep Kumar Samal, Sung Kyu Lim, and Yiyu Shi, “A Novel Entropy Production Based Full-Chip TSV Fatigue Analysis”, IEEE International Conference on Computer-Aided-Design (ICCAD), 2015.
  9. Sandeep Kumar Samal, Yang Li, GuoQing Chen, and Sung Kyu Lim, “Improving Performance in Near- Threshold Circuits Using 3D IC Technology”, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015.
  10. Deepak Nayak, Srinivasa Banna, Sandeep Kumar Samal, and Sung Kyu Lim, “Power, Performance, and Cost Comparisons of Monolithic 3D ICs and TSV-based 3D ICs”, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015.
  11. Sandeep Kumar Samal, Kambiz Samadi, Pratyush Kamal, Yang Du, and Sung Kyu Lim, “Full Chip Impact Study of Power Delivery Network Designs in Monolithic 3D ICs“, IEEE International Conference on Computer-Aided Design (ICCAD), 2014.
  12. Shreepad Panth, Sandeep Kumar Samal, Yun Seop Yu, and Sung Kyu Lim, “Design Challenged and Solutions for Ultra-High-Density Monolithic 3D ICs”, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2014 (Invited Paper).
  13. Sandeep Kumar Samal, Yarui Peng, and Sung Kyu Lim, “Design and Analysis of Ultra Low Power Processors Using Sub/Near-Threshold 3D Stacked ICs”, SRC TECHON Conference, 2014.
  14. Sandeep Kumar Samal, Shreepad Panth, Kambiz Samadi, Mehdi Saeidi, Yang Du and Sung Kyu Lim, “Fast and Accurate Thermal Modeling and Optimization for Monolithic 3D ICs”, ACM Design Automation Conference (DAC) 2014.
  15. Sandeep Kumar Samal, Kiyoung Kim, Youngchan Kim, Taesung Kim, Hyuk-Jae Lee, Taewhan Kim and Sung Kyu Lim, “Ultra Low Power 2-tier 3D Stacked Sub-threshold H.264 Intra Frame Encoder“, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2013.
  16. Sandeep Kumar Samal, Yarui Peng, Yang Zhang and Sung Kyu Lim, “Design and Analysis of Ultra Low Power Processors Using Sub/Near-Threshold 3D Stacked ICs“, IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2013
  1. Sandeep Kumar Samal and Sung Kyu Lim, “Design and CAD Solutions for Cooling and Power Delivery for Monolithic 3D ICs”, in Handbook of 3D Integration, Vol 4: Design, Test and Thermal Management, edited by Paul Franzon et al, Wiley-VCH, 2019. (ISBN 978-3-5273-3855-9).
  2. Sandeep Kumar Samal and Sung Kyu Lim, “Ultralow Power Processor Design with 3D IC Operating at Sub/Near-Threshold Voltages”, in CISS: Nano Devices and Circuit Techniques for Low-Energy Applications and Energy Harvesting, edited by Chong-Min Kyung, Springer, 2015 (ISBN 978-94-017-9989-8).

PhD: Georgia Institute of Technology, Electrical and Computer Engineering, 2017

B.Tech: Indian Institute of Technology Kharagpur, Electronics and Electrical Communication Engineering, 2012

  • Visiting Assistant Professor, IIT Bhubaneswar (Jun 2025 onwards)
  • FPGA Silicon Design Engineer, Altera Corporation, USA (Jan 2024 to May 2025)
  • SoC Design Engineer, Intel Corporation, USA (Jun 2017 to Dec 2023)
  • Graduate Research Intern, Globalfoundries, USA (May 2015 to Apr 2016)
  • Multiple Divisional Recognition Awards (DRA) inside Intel Corporation, USA
  • Finalist in Qualcomm Innovation Fellowship (QInF), USA in 2016 and 2014
  • MITACS Globalink Award for Internship at The University of Western Ontario, Canada, 2011
  • Young Engineer and Scientist (YES) Award by Honda Motor Company, Japan, 2010-11
  • Jagadish Bose National Science Talent Search (JBNSTS) Scholarship 2008-12
  • Fourth rank in Odisha state Higher Secondary Examination (CHSE), 2008
  • Indian National Chemistry Olympiad (INChO) Gold Medal 2008
  • Top 1% in India in National Standard Examination in Physics, 2008
  • Top 1% in India in National Standard Examination in Chemistry, 2008
  • Fourth rank in Odisha state Regional Mathematics Olympiad (RMO), 2006-07
  • Kishore Vaigyanik Protsahan Yojna (KVPY) Fellowship, 2006-08
  • National Talent Search Examination (NTSE) Scholarship, 2006
  • Senior Member, IEEE
  • Conference Committees
    • Design Automation Conference (DAC) 2015-2025, TPC (2023-ongoing), DFM Session Co-Chair in DAC 2023
    • VLSI Design Conference (VLSI-D), 2026, EDA/CAD Track Co-chair
  • Journal Peer Review
    ▪ IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (IEEE TCAD)
    ▪ IEEE Transactions on Nanotechnology (IEEE TNANO)
    ▪ IEEE Access
    ▪ Micro and Nano Letters
    ▪ Engineering Optimization
Scroll to Top