Manoranjan Satpathy – School of Electrical and Computer Sciences

Prof. Manoranjan Satpathy

Professor

Software Testing & Verification; Software Engineering; Formal Methods; High Performance Computing Systems

Past scholars:

1) Daniel Rodriguez Garcia, University of Reading

[co-supervision with Prof Rachel Harrison]

(Now Associate Professor, University of Alcala, Spain)

2) H.K. Mishra, Utkal University

[co-supervision with Prof B. Mohanty]

(now Professor, IRMA, Anand)

3) Debiprasanna Sahoo, IIT Bhubaneswar, degree awarded in 2019

(now Asst Professor, IIT Roorkee)

4) Shivani Tripathy, IIT Bhubaneswar, degree awarded in 2022

(now with AMD, Bangalore)

Present Scholars:

1) Anik Chaudhury, IIT Bhubaneswar

2) Mitali Sihna, IIT Bhubaneswar

(co-spervision with Dr Padmalochan Bera)

Author(s)	Recent Publication (International Journals)
S. Tripathy, D. Sahoo, M. Satpathy, Madhu Mutyam	1 Formal Modeling and Verification of Security Properties of a Ransomware-Resistant SSD. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, DOI: 10.1109/TCAD.2022.3229596,2022.
S. Behera, D.P. Dogra, M. Satpathy	2 Effect of migrant labourer inflow on the early spread of Covid-19 in Odisha: A case study, In ACM Transactions on Spatial Algorithms and Systems (TSAS), Vol 8(4), pp 1-18, 2022.
S. Tripathy, M. Satpathy	3 SSD internal cache management policies: A survey, In Journal of System Architecture, Elsevier, Vol 122:102334, 2022.
A. Choudhury, A. Mohanty, M. Satpathy	4 A Parallizable Model for Analysing Cancer Tissue Heterogeneity, In IEEE/ACM Transactions on Computational Biology and Bioinformatics (TCBB), doi: 10.1109/TCBB.2021.3085894,2021.
D. Sahoo, S. Sha, M. Satpathy, Madhu Mutyam	5 Formal Modeling and Verification of a Victim DRAM Cache, In ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol 24, pp.1-20, 2019.
D. Sahoo, S. Sha, M. Satpathy, Madhu Mutyam	6 ReDRAM: A Reconfigurable DRAM Cache for GPGPU, IEEE Computer Architecture Letters, Vol 17, pp. 213-216, 2018
D. Sahoo, Madhu Mutyam, M. Satpathy, S. Sha, S. Ramesh, P. Roop	7 Formal Modeling and Verification of Controllers for a Family of DRAM Caches, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 37, pp. 2485-2496, 2018.
S. Biswas, R. Mall, M. Satpathy	8 A Regression Test Selection Technique for Embedded Software, to appear in ACM Transactions on Embedded Computing Systems.
M. Satpathy, A. Yeolekar, P. Peranandam, S. Ramesh	9 Efficient coverage of parallel and hierarchical Stateflow models for test case generation, Journal of Software Testing, Verification and Reliability, Wiley Interscience, Vol. 22(7), pp. 457-479, September 2012.
S. Biswas, R. Mall, M. Satpathy	10 Task Dependency Analysis for regression test selection of Embedded Programs, IEEE Embedded System Letters, V 3(4), 2011, pp.117-120
S. Biswas, R. Mall, M. Satpathy, S. Sukumaran	11 Regression Test Selection Techniques: A Survey, Journal Informatica, published by Slovenia Society of Informatics, Vol 35(2011), 289-321.
R. Suman, R. Mall, S. Sukumaran, M. Satpathy	12 Extracting state models for black-box software components, Journal of Object Technology, published by ETS Zurich, Vol 9(3): 79-103, 2010.
L. Tsiopoulos, M. Satpathy	13 Model based testing of a Network-on-Chip component, Electronics Notes on Theoretical Computer Science, Elsevier, 253(2):101-116, 2009.
H.K. Misra, M. Satpathy, H. Mohanty	14 Measuring user’s role to assess organization preparedness in a systems acquisition life cycle: a cognitive framework, Intnl. Journal of Information and Communication Technology, Inderscience publichers, Vol 1(1), pp. 50-61, 2007.
M. Satpathy, M. Leuschel , M. Butler	15 ProTest: An Automatic Test Environment for B Specifications, Electronics Notes on Theoretical Computer Science (ENTCS), Elsevier, (111): 113-136, 2005.
NT Siebel, S. Cook, M. Satpathy, D. Rodriguez	16 Latitudinal and longitudinal process diversity, Journal of Software Maintenance and Evolution, John Wiley, Vol. 15(1), 9-25, 2003.
S. Mishra, K Sikdar, M. Satpathy	17 Optimizing register spills for eager functional languages, Future Generation Computer Systems, Elsevier, Vol 18(5): 699-708, 2002. Elsevier
M. Satpathy, A. Sanyal, G. Venkatesh	18 Improved Register Usage for Functional Program through Multiple Function Versions, Journal of Functional and Logic Programming (JFLP) Vol 1998(7), MIT Press, 1998.

Recent Publication (International Conferences)	Author(s)/Speaker(s)
An Anomaly Free Distributed Firewall System for SDN. IEEE Cyber Science Conference, Dublin, 2021: 1-8.	M. Sinha, P. Bera, M. Satpathy
LocalityGuru: A PTX Analyzer for Extracting Thread Block-level Locality in GPGPUs. IEEE Networking Architecture and Storage Conference, Riverside (NAS 2021): 1-8, 2021.	D. Tripathy, AmirAli Abdolrashidi, Quan Fan, Daniel Wong, M Satpathy
Fuzzy fairness controller for NVMe SSDs, ACM International Conf on Supercomputing (ICS), Barcelona, 2020.	S Tripathy, D. Sahoo, M. Satpathy, Madhu Mutyam
Slumber: static-power management for GPGPU register files, ACM/IEEE International Symposium on Low Power Electronics (ISLPED), Vol 1, 2020.	D. Tripathy, L.N. Bhuyan, Hadi Zamani, D Sahoo, M. Satpathy
Formal Modelling and Verification of NAND Flash Memory, IEEE ICCD (Intnl Conf on omputer Design), Abu Dhabi, 2019, pp. 1-4.	S. Tripathy, D. Sahoo, M. Satpathy, S. Pinnisety
Post-Model Validation of Victim DRAM Caches, IEEE ICCD (Intnl Conf on omputer Design), Abu Dhabi, 2019, pp. 5-8.	D. Sahoo, S. Tripathy, M. Satpathy and M. Mutyam
7. Multidimensional Grid Aware Address Prediction for GPGPU, IEEE International Conference on VLSI Design (VLSID), New Delhi, 2019,pp:263-268.	S. Tripathy, D. Sahoo and M. Satpathy
CAMO: A Novel Cache Management Organization for GPGPUs, IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), 2018, pp. 215-220.	D. Sahoo, S. Sha, M. Satpathy, M. Mutyam and L. N. Bhuyan
Locking Lines in Tag Cache to Improve Access Optimization for DRAM Caches:WIP, IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), ESWEEK, Turin, 2018.	S. Tripathy, D. Sahoo and M. Satpathy
An Experimental Study on Dynamic Bank Partitioning of DRAM in Chip Multiprocessors, 30th IEEE International Conference on VLSI Design (VLSID), Hyderabad, 2017, pp. 35-40.	D. Sahoo, M. Satpathy and M. Mutyam
MSimDRAM: Formal Model Driven Development of a DRAM Simulator, IEEE VLSI Design Conference, 2016.	D. Sahoo, M. Satpathy
Sensors in your clothes: Design and Development of a Prototype, Mobile Web an Intelligence Information Systems (MobiWIS), Viena, pp. 302-312,2016.	K.Lorentzen,T. Gronli,G. Ghinea,M. Younas, M. Satpathy
Inferring State Models using Feedback Directed-Random Testing, IEEE Asia Pacific Software Engineering Conference, pp. 322-329, 2014.	S. Sukumaran, M Satpathy, S K Kolluru, R Mall
Architectural semantics of AADL using Event-B, 2014 International Conference on Contemporary Computing and Informatics (IC3I), Bangalore, IEEE, 2014.	M D’Souza ; S. Ramesh ; M Satpathy
A Mixed Approach to Rigorous Development of Control Designs, to appear in the Proc. of the IEEE Conf. on Computer Aided Control Design â€“ Systems under uncertainty (CSCSD-SU), Hederabad, August 2013.	M Satpathy, S Ramesh, C. Snook, NK Singh, M. Butler
Systematic Development of Control Designs via Formal Refinement, Proc. of the International Conf. on Model Driven Engineering and Software Development, Barcelona, Feb 2013.	M.Satpathy, C. Snook, S. Arora, S. Ramesh, M. Butler
SmartTestGen+: A Test suite booster for enhanced structural coverage, Intnl. Colloquium in Theoretical Aspects of Computing (ICTACâ€™12), LNCS Volume 7521, September 2012.	S. Raviram, P. Peranandam, M. Satpathy, S. Ramesh
SmartTestGen: An integrated test generation framework for enhanced coverage of Simulink/Stateflow models, IEEE Design Automation & Test in Europe Conf. (DATEâ€™12), pp. 308-311, 2012	P. Peranandam, S. Raviram, M. Satpathy, A. Yeolekar, A. Gadkari, S. Ramesh
Cross-layer analysis, testing and verification of automotive control software, in Proc. of ACM EMSOFTâ€™11 (International Conference on Embedded Software), pp. 263-272, 2011.	M. Broy, S. Chakrabarty, D. Goswami, S. Ramesh, M. Satpathy, S. Resmeretia, W. Pree
Formal foundation to systematic development of Simulink/Stateflow models, Proc. of the Dagstuhl Seminar on Refinement based methods for the construction of dependable systems, 2009.	M. Satpathy, S. Ramesh
Randomized Directed Testing (REDIRECT) for Simulink/Stateflow models, in Proc. of ACM EMSOFTâ€™08 (International Conference on Embedded Software), 2008, pp. 217-226.	M. Satpathy, A. Yeolekar, S. Ramesh
Test case generation from formal models through abstraction refinement and model checking, ACM workshop on Advances in Model Based Testing (A-MOST), 2007	M. Satpathy, S. Ramesh
Automatic Testing from Formal Specifications, in Proc. of Intnl. Conf. on Testing and Proofs (TAPâ€™07), LNCS 4454, pp. 95-113, 2007.	M. Satpathy, M. Butler, M. Leuschel, S. Ramesh
Synthesis of Scenario Based Test Cases from B Models, in Proc. of FATES/RV 2006 (Formal Approaches to Software Testing and Runtime Verification, LNCS. 4262, Springer, pp. 133-147, 2006.	M. Satpathy, Q. Malik, J. Lilius
A Formal Model of Context-Awareness and Context-Dependency, IEEE SEFMâ€™06 (Software Engineering and Formal Methods), 177-185, 2006.	M. Neovius, K. Sere, L. Yuan, M. Satpathy
Refactoring of Assertions in Design by Contract, Internl. Workshop on Object-Oriented Reengineering (WOOR2006), in conjuntion with the European Conference on Object-Oriented Programming (ECOOP), Nantes, 2006.	D. RodrÃguez, M. Satpathy, J. Coves, J.J. Cuadrado
Managing Information Technology Acquisition in Organizations: a Strategic Evaluation Framework, e-Commerce 2005 Proceedings, 2005.	H.K. Misra, M. Satpathy, B. Mohanty
Assertions in Object Oriented Software Maintenance: Analysis and a Case Study, IEEE ICSMâ€™04 (International Conference on Software Maintenance), 2004, pp. 124-135.	M. Satpathy, N.T. Siebel, D. Rodriguez
Effective Software Project Management Education through Simulation Models: An Externally Replicated Experiment, Proc of PROFES (Product Focused Process Improvement), LNCS 3009, Springer, 287-301, 2004.	D. Rodriguez, M. Satpathy, D. Pfahl
High Performance Code Generation through Lazy Activation Records, IEEE Workshop on INTERACT (Interaction between in Compilers and Computer Architectures), 2003, pp. 37-50,	M.Satpathy, RN Mahapatra, S. Choudhury, S. Chitnis
A Typed Generic Process Model for Product Focused Process Improvement, IEEE COMPSACâ€™02, pp.379-384. 2002.	M. Satpathy, R. Harrison
An Investigation of Prediction Models for Project Management, IEEE COMPSACâ€™02 (Conference on Computer Science and Applications), pp. 779-784.	D. Rodriguez, R. Harrison, M. Satpathy, J. Dolado
Maintenance of Object Oriented Systems through Re-Engineering: A Case Study, IEEE ICSMâ€™02 (Intnl. Conf on Software Maintenance), pp. 540-549.	M. Satpathy, N.T. Siebel, D. Rodriguez
Generic Model and Tool Support for Assessing and Improving Web Processes, IEEE METRICSâ€™02 (Intnl . Software Metrics Symposium), pp. 141-151.	D. Rodriguez, R. Harrison, M. Satpathy
A Comparative Study of Formal and Informal Specifications through an Industrial Case Study, Proc IEEE/IFIP Workshop on Formal Specification of Computer Based Systems (FSCBSâ€™01), 2001.	M. Satpathy, R. Harrison, C. Snook, M. Butler
Tool support for the typed generic process model, In Current Trends in Software Measurement (Dumke, Abran (eds)), Proc. 11thInternational Workshop on Software Measurement, (IWSMâ€™01), Shaker Verlag, 2001.	D. Rodriguez, R. Harrison, M. Satpathy
A Generic Model for Assessing Process Quality, Intnl Workshop on Software Measurement (IWSMâ€™2000), LNCS No. 2006, Springer, pp. 94-110, 2000.	M. Satpathy, R. Harrison, C. Snook, M. Butler
Some Decidability Results for Duration Calculus under Synchronous Interpretation, FTRTFTâ€™98 (Formal Techniques in Real-Time and Fault Tolerant Systems), LNCS 1486, Springer, pp. 186-197, 1998.	M. Satpathy, DV Hung, PK Pandya
Automaton-Driven Frame Disposal Algorithm and its Proof of Correctness, ASIAN 1995 (Asian Computer Science Conference), LNCS 1023, Springer, pp. 88-102, 1995.	M. Satpathy, A. Sanyal, G. Venkatesh
Rationalized Three Instruction Machine, ACM POPL workshop on Intermediate Representation (IRâ€™95), Sigplan Notices special issue, pp. 94-102, 1995.	SV Chitnis, M. Satpathy, S. Oberoi
Improved Compilation of Functional Programs through Voltage Graphs, National seminar on Theoretical Computer Science, 1995.	M. Satpathy, A. Sanyal

Degree	Discipline	Year	School
Ph.D	Computer Science	1997	IIT Bombay

Staff Reseracher General Motors India Science Lab, Bangalore [2006-2012]

Post doctoral Reseracher Abo Akademi, Finland [2005-2006]

Lecturer Department of Computer Science University of Reading [1999-2005]

Asst Professor Department of Computer Science and Engg IIT Guwahati [1997-1999]

Programmer Analyst Tata Motors, Jamshedpur [1987-1990]

Best Poster award at the IEEE Asia and South Pacific Design Automation Conference
Discovery Project Award from Global General Motors R&D

8 years of Teaching + 7 years in industry